In the previous post, we added an inverter, a 2-input NAND, and a 2-input NOR into our library.In this post, I shall add a few more cells into my library. I am choosing to add these cells mainly because, in my experience, these are the cells that are mostly used by the tools to synthesize your behavioral logic to a structural description. This is not the perfect library of cells, and I will want to add more custom cells in the future. These cells are more like a template upon which I will want to build my library.

There is this wonderful paper online which argues that a library with 20 cells can perform almost as well as a library with 400 cells. It's called

Compact yet high-performance (CyHP) library for short time-to-market with new technologies

Read through this paper once before choosing to build your library.

The cells I will be adding to my library are:

1. TIEHI

2. TIELO

3. AOI21

4. OAI21

5. MUX2

6. NAND3

7. NOR3

8. XOR2

9. XOR3

10. XNOR2

11. XNOR3

This is quite a few cells, but building the schematics for these guys should not take more than 5 minutes even if you are new to the tools. Alright then, let's build us a library!

1. TIEHI

A big chunk of the real estate in today's microprocessors (almost 50% if not bigger) is made up of memory. The parameter we use to test the performance of memories is noise margins, which is a measure of how much noise a memory cell can handle before it corrupts the stored bit. Reduced supply voltage means that the noise margins are reduced. The power supply rails in a chip contribute some noise to the logic. We have IR drops and di/dt noise. Power supply rails are made up of metal, and so we have IR drop across the metal over distances. The di/dt noise is when a certain logic is unused, and then it suddenly becomes active, drawing current in a small period of time. This creates a large di/dt which introduces noise into the circuit.

TIEHI and TIELO are cells we build to counter this problem. TIEHI is a cell which always supplies a Vdd at its output. There is no input, only one output which is always Vdd. This is the cell we use to power our logic rather than power it off the supply rail. The same is with TIELO, which always outputs a gnd.

The schematic shows a TIEHI circuit. Notice the Gate and drain terminals of the nmos are connected together. This is what we call as diode-connect of a transistor, and ensures that the transistor is always saturated. Another property of such a device is that it has a large forward current but a very small reverse leakage current. Hence the name diode-connect!

The symbol above represents a TIEHI cell.

2. TIELO

3. MUX2

Mux's are amazing circuits, and I absolutely love them. A 2 input mux performs an if else statement.

Y=~SA + SB; When we read this logic, it is

if(S==0) { then pass A}

else {pass B};

The mux logic is unique in the sense that it can be used to generate a wide array of logic, as we will see later with xor's and other logic. This also translates to an incredible reduction in the number of transistors used, which is always desired in VLSI, where you want to be able to cram more logic into a small space. There are a number of ways of implementing a 2:1 MUX. The PMOS's are 3u and NMOS's are 1.5u each.

Here is the symbol for a 2:1 MUX.

4. OAI21 and AOI21

OAI stands for OR-AND-INVERT; and AOI stands for AND-OR-INVERT.

So, OAI21 logic is Y = ~[(A+B)C] and AOI21 is Y = ~[A.B+C].

The reason we use these gates a lot is because they perform some pretty complicated logic but use only 6 transistors. You'll be surprised as to how much the synthesis tools use these gates to "structurize" your behavioral. So, if the chip you are building has some sort of an ALU, then these gates are an absolute must!

The pictures below shows the schematic and symbol for a OAI21 and AOI21.

Feel free to go crazy on your symbols! Sizing of transistors are very important. Ideally, you want equal resistance for Pull-up and Pull-down. This however is not the case when you are building your own custom schematics, and you know exactly why you undersize / oversize your circuit.

For the OAI and AOI, i will size them ti have equal Pull-up and Pull-down resistance. The next post will discuss transistor sizing for different architectures in detail.

OAI21 Schematic:

OAI21 Symbol:

AOI21 Schematic:

AOI21 Symbol:

5. NAND3 and NOR3

For a NAND3, Y=~(A&B&C), and for a NOR3, Y=~(A|B|C).

NAND3 Schematic and Symbol:

NOR3 Schematic and Symbol:

6. XOR2 and XOR3

XORs are very interesting gates. They are extensively used to perform the addition of 2/3 inputs, and so any ALU/Processor block you see will have multiple XORs in their design. This also means that our XORs should be compact, and perform brilliantly. One way of implementing a XOR gate is similar to how our NAND and NOR is implemented. This uses 12 gates. Another way is to use a MUX2 and INV. This implements the same function, but uses only 8 gates. So, you have a 33% improvement in area, and power consumed right off the bat.

XOR2 Schematic and Symbol:

XOR3 Schematic and Symbol:

7. XNOR2 and XNOR3

XNORs are XORs followed by an INV. Or, another way of building XNOR is use an XOR gate, but interchange inputs to A and B. See the schematic for a better understanding.

XNOR2 Schematic and Symbol: